CY7C1333H
PRELIMINARY
2-Mbit (64K x 32) Flow-Through SRAM
with NoBL™ Architecture
• Low standby power
Features
Functional Description[1]
• Can support up to 133-MHz bus operations with zero
wait states.
The CY7C1333H is a 3.3V, 64K x 32 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1333H is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
— Data is transferred on every clock.
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use
OE
• Registered inputs for flow-through operation
• Byte Write capability
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
• 64K x 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 8.0 ns (for 100-MHz device)
Write operations are controlled by the two Byte Write Select
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes Offered in Lead-Free
• Asynchronous Output Enable
(BW
) and a Write Enable (WE) input. All writes are
[A:D]
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE , CE , CE ) and an
1
2
3
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
• Offered in Lead-Free JEDEC-standard 100 TQFP
package
• Burst Capability—linear or interleaved burst order
Logic Block Diagram
ADDRESS
A0, A1, A
REGISTER
A1
A1'
Q1
D1
A0
A0'
Q0
D0
MODE
C
BURST
LOGIC
CE
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD
BWA
BWB
BWC
BWD
WE
A
B
U
F
MEMORY
ARRAY
WRITE
DRIVERS
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
A
M
P
F
E
R
S
S
E
N
G
INPUT
REGISTER
E
OE
CE1
CE2
CE3
READ LOGIC
SLEEP
Control
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-00209 Rev. **
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 11, 2005
CY7C1333H
PRELIMINARY
Pin Definitions (100-pin TQFP Package)
Name
I/O
Description
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge
are fed to the two-bit burst counter.
A , A , A
Input-
0
1
Synchronous of the CLK. A
[1:0]
Input-
Byte Write Inputs, active LOW. Qualified with WE to conduct Writes to the SRAM. Sampled on
BW
[A:D]
Synchronous the rising edge of CLK.
Input-
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
WE
Synchronous signal must be asserted LOW to initiate a Write sequence.
Input-
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
ADV/LD
Synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD should be
driven LOW in order to load a new address.
CLK
Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
CE
1
Synchronous CE , and CE to select/deselect the device.
2
3
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
2
Synchronous CE and CE to select/deselect the device.
1
3
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
3
Synchronous CE and CE to select/deselect the device.
1
2
Input-
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
OE
Asynchronous inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins.
OE is masked during the data portion of a Write sequence, during the first clock when emerging
from a deselected state, when the device has been deselected.
Input-
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
CEN
ZZ
Synchronous SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Input-
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. During normal operation, this pin can be connected to V or left
SS
floating.
DQ
I/O-
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
s
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by address during the clock rise of the Read cycle. The direction of the pins is controlled
by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs.
When HIGH, DQ are placed in a three-state condition. The outputs are automatically three-stated
s
during the data portion of a Write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
Mode
Input
Strap Pin
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. Whentiedto V or left floating selects interleaved
DD
burst sequence.
V
V
Power Supply Power supply inputs to the core of the device.
DD
I/O Power
Supply
Power supply for the I/O circuitry.
DDQ
V
Ground
–
Ground for the device.
SS
NC
No Connects. Not Internally connected to the die.
4M, 9M,18M,36M, 72M, 144M, 256M, 576M and 1G are address expansion pins and are not
internally connected to the die.
Document #: 001-00209 Rev. **
Page 3 of 12
CY7C1333H
PRELIMINARY
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Functional Overview
The CY7C1333H is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,
1
2
and CE are ALL asserted active, and (3) the write signal WE
3
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically three-stated regardless of the state of the OE
input signal. This allows the external logic to present the data
on DQs.
rise (t
) is 6.5 ns (133-MHz device).
CDV
Accesses can be initiated by asserting all three Chip Enables
(CE , CE , CE ) active at the rising edge of the clock. If Clock
1
2
3
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
On the next clock rise the data presented to DQs (or a subset
for Byte Write operations, see Truth Table for details) inputs is
latched into the device and the write is complete. Additional
accesses (Read/Write/Deselect) can be initiated on this cycle.
the status of the Write Enable (WE). BW
conduct Byte Write operations.
can be used to
[A:D]
The data written during the Write operation is controlled by
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
BW
signals. The CY7C1333H provides Byte Write
[A:D]
capability that is described in the Truth Table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input will selectively write to only the desired bytes. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed Write mechanism has been
provided to simplify the Write operations. Byte Write capability
has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.
Three synchronous Chip Enables (CE , CE , CE ) and an
1
2
3
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
Because the CY7C1333H is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE) can be deasserted HIGH
before presenting data to the DQ inputs. Doing so will
three-state the output drivers. As a safety precaution, DQs are
automatically three-stated during the data portion of a Write
cycle, regardless of the state of OE.
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,
1
2
and CE are ALL asserted active, (3) the Write Enable input
3
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
Burst Write Accesses
The CY7C1333H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE , CE , and CE ) and WE inputs are
1
2
3
ignored and the burst counter is incremented. The correct
BW inputs must be driven in each cycle of the burst write,
[A:D]
in order to write the correct bytes of data.
Burst Read Accesses
Sleep Mode
The CY7C1333H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A and A in the burst sequence, and will
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE , CE , and CE , must remain inactive
0
1
1
2
3
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enable inputs or WE. WE is latched at the
for the duration of t
after the ZZ input returns LOW.
ZZREC
Document #: 001-00209 Rev. **
Page 4 of 12
CY7C1333H
PRELIMINARY
Interleaved Burst Sequence
Linear Burst Address Table (MODE = GND)
First
Second
Third
Fourth
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Address
Address
Address
A1, A0
10
Address
Address
A1, A0
A1, A0
00
A1, A0
01
A1, A0
11
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min.
Max.
40
Unit
mA
ns
I
t
t
t
t
ZZ > V − 0.2V
DD
DDZZ
ZZ > V − 0.2V
2t
ZZS
DD
CYC
ZZ < 0.2V
2t
ns
ZZREC
ZZI
CYC
ZZ Active to sleep current
ZZ inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2t
ns
CYC
0
ns
RZZI
Truth Table[2, 3, 4, 5, 6, 7, 8]
ADDRESS
Operation
Deselect Cycle
Deselect Cycle
Deselect Cycle
Used
None
None
None
None
CE
H
CE2 CE
ZZ
L
ADV/LD
WE BW
X
OE CEN CLK
DQ
1
3
X
X
L
X
H
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L->H Three-State
L->H Three-State
L->H Three-State
L->H Three-State
X
L
X
L
L
Continue Deselect
Cycle
X
X
L
H
READ Cycle
(Begin Burst)
External
Next
L
X
L
H
X
H
X
H
X
H
X
X
X
L
X
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
X
H
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
H
X
L->H Data Out (Q)
L->H Data Out (Q)
L->H Three-State
L->H Three-State
L->H Data In (D)
L->H Data In (D)
L->H Three-State
L->H Three-State
READ Cycle
(Continue Burst)
NOP/DUMMY READ
(Begin Burst)
External
Next
H
H
X
X
X
X
X
X
DUMMY READ
(Continue Burst)
X
L
X
L
H
L
WRITE Cycle
(Begin Burst)
External
Next
WRITE Cycle
(Continue Burst)
X
L
X
L
H
L
X
L
L
NOP/WRITE ABORT
(Begin Burst)
None
H
H
X
X
WRITE ABORT
(Continue Burst)
Next
X
X
X
X
X
X
H
X
X
X
X
X
IGNORE CLOCK
EDGE (Stall)
Current
None
L->H
X
-
Sleep MODE
Three-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
Selects are asserted, see Truth Table for details.
3. Write is defined by BW
, and WE. See Truth Table for Read/Write.
[A:D]
4. When a Write cycle is detected, all I/Os are three-stated, even during Byte Writes.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle DQ = Three-state when OE is inactive
s
or when the device is deselected, and DQ = data when OE is active.
s
Document #: 001-00209 Rev. **
Page 5 of 12
CY7C1333H
PRELIMINARY
Truth Table for Read/Write[2, 3]
Function
BW
BW
BW
BW
D
WE
A
B
C
Read
H
X
H
L
X
X
X
Write No Bytes Written
L
L
L
L
L
L
H
H
L
H
H
H
L
H
H
H
H
L
Write Byte A – (DQ )
A
Write Byte B – (DQ )
H
H
H
L
B
Write Byte C – (DQ )
H
H
L
C
Write Byte D – (DQ )
H
L
D
Write All Bytes
L
Document #: 001-00209 Rev. **
Page 6 of 12
CY7C1333H
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Range Temperature (T )
Supply Voltage on VDD Relative to GND ...... –0.5V to +4.6V
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V
V
V
DDQ
A
DD
Com’l
Ind’l
0°C to +70°C 3.3V – 5%/+10% 3.3V – 5% to
+ 0.5V
V
DDQ
DD
-40°C to +85°C
DC Input Voltage....................................–0.5V to V + 0.5V
DD
[9,10]
Electrical Characteristics Over the Operating Range
Parameter
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min.
3.135
3.135
2.4
Max.
Unit
V
V
3.6
DD
DDQ
OH
OL
IH
V
V
V
V
V
I
for 3.3V I/O
for 3.3V I/O, I = –4.0 mA
V
V
DD
V
OH
for 3.3V I/O, I = 8.0 mA
0.4
+ 0.3V
V
OL
for 3.3V I/O
for 3.3V I/O
2.0
–0.3
–5
V
V
DD
[9]
Input LOW Voltage
0.8
V
IL
Input Load Current (except GND ≤ V ≤ V
ZZ and MODE)
5
µA
X
I
DDQ
Input Current of MODE
Input = V
Input = V
Input = V
Input = V
–30
–5
µA
µA
SS
DD
SS
DD
5
Input Current of ZZ
µA
30
5
µA
I
I
Output Leakage Current
GND ≤ V ≤ V , Output Disabled
–5
µA
OZ
I
DD
V
Operating Supply
V
f = f
= Max., I
= 0 mA,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
225
205
90
mA
mA
mA
mA
DD
DD
DD
OUT
Current
= 1/t
MAX CYC
I
I
I
I
Automatic CE Power-down V = Max, Device Deselected, 7.5-ns cycle, 133 MHz
DD
Current—TTL Inputs
SB1
V
≥ V or V ≤ V , f = f
,
IN
IH
IN
IL
MAX
10-ns cycle, 100 MHz
80
inputs switching
Automatic CE Power-down V = Max, Device Deselected, All speeds
Current—CMOS Inputs
40
mA
SB2
SB3
SB4
DD
V
≥ V – 0.3V or V ≤ 0.3V,
IN DD IN
f = 0, inputs static
Automatic CE Power-down V = Max, Device Deselected, 7.5-ns cycle, 133 MHz
Current—CMOS Inputs
75
65
mA
mA
DD
V
≥ V
MAX
– 0.3V or V ≤ 0.3V,
IN
DDQ IN
, inputs switching
10-ns cycle, 100 MHz
f = f
Automatic CE Power-down V = Max, Device Deselected, All speeds
45
mA
DD
Current—TTL Inputs
V
≥ V – 0.3V or V ≤ 0.3V,
IN DD IN
f = 0, inputs static
Thermal Resistance[11]
100 TQFP
Package
Parameters
Description
Test Conditions
Unit
Θ
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
30.32
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
6.85
°C/W
JC
Notes:
9. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC)> –2V (Pulse width less than t /2).
CYC
IH
DD
CYC
IL
10. Power-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
IH
DD
DDQ
DD
11. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-00209 Rev. **
Page 7 of 12
CY7C1333H
PRELIMINARY
Capacitance[11]
Parameter
Description
Input Capacitance
Clock Input Capacitance
I/O Capacitance
Test Conditions
100 TQFP Package
Unit
pF
C
C
C
T = 25°C, f = 1 MHz,
5
5
5
IN
A
V
= 3.3V
DD
pF
CLOCK
I/O
V
=3.3V
DDQ
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
[12, 13]
Switching Characteristics Over the Operating Range
133 MHz
100 MHz
Parameter
Description
Min.
Max.
Min.
Max.
Unit
[14]
t
V
(Typical) to the First Access
1
1
ms
POWER
DD
Clock
t
t
t
Clock Cycle Time
Clock HIGH
7.5
2.5
2.5
10
4.0
4.0
ns
ns
ns
CYC
CH
Clock LOW
CL
Output Times
t
t
t
t
t
t
t
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
6.5
8.0
ns
ns
ns
ns
ns
ns
ns
CDV
2.0
0
2.0
0
DOH
CLZ
[15, 16, 17]
Clock to Low-Z
15, 16, 17]
Clock to High-Z
3.5
3.5
3.5
3.5
CHZ
OEV
OELZ
OEHZ
OE LOW to Output Valid
[15, 16, 17]
OE LOW to Output Low-Z
0
0
[15, 16, 17]
OE HIGH to Output High-Z
3.5
3.5
Set-up Times
t
t
t
t
t
t
Address Set-up before CLK Rise
ADV/LD Set-up before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
AS
ALS
WES
CENS
DS
WE, BW
Set-up before CLK Rise
[A:D]
CEN Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
CES
Notes:
12. Timing reference level is 1.5V when V
=3.3V
DDQ
13. Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
14. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V minimum initially before a Read or Write operation
POWER
DD
can be initiated.
15. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
16. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions
17. This parameter is sampled and not 100% tested.
Document #: 001-00209 Rev. **
Page 8 of 12
CY7C1333H
PRELIMINARY
[12, 13]
Switching Characteristics Over the Operating Range (continued)
133 MHz
Min. Max.
100 MHz
Parameter
Hold Times
Description
Min.
Max.
Unit
t
t
t
t
t
t
Address Hold after CLK Rise
ADV/LD Hold after CLK Rise
WE, BW Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
ALH
WEH
CENH
DH
[A:D]
CEN Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
CEH
Switching Waveforms
[18, 19, 20]
Read/Write Waveforms
t
1
2
3
4
5
6
7
8
9
10
CYC
t
CLK
CEN
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CE
ADV/LD
WE
BW[A:D]
A1
A2
A4
A3
CDV
A5
A6
A7
ADDRESS
DQ
t
t
t
AS
AH
t
t
t
t
DOH
OEV
CLZ
CHZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
For this waveform ZZ is tied LOW.
18.
19. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
20. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 001-00209 Rev. **
Page 9 of 12
CY7C1333H
PRELIMINARY
Switching Waveforms (continued)
[18, 19, 21]
NOP, STALL and DESELECT Cycles
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW[A:B]
ADDRESS
A1
A2
A3
A4
A5
t
CHZ
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
DOH
DQ
t
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
[22, 23]
ZZ Mode Timing
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
133
CY7C1333H-133AXC
CY7C1333H-133AXI
CY7C1333H-100AXC
CY7C1333H-100AXI
A101
A101
A101
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Industrial
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Industrial
100
Shaded area contains advance information. Please contact your local Cypress sales representative for availability of this part.
21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
22. Device must be deselected when entering ZZ mode. See Truth Table for all possible signal conditions to deselect the device.
23. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 001-00209 Rev. **
Page 10 of 12
PRELIMINARY
CY7C1333H
Package Diagram
100-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
NoBL and No Bus Latency are trademarks of Cypress Semiconductor. ZBT is a trademark of Integrated Device Technology. All
product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 001-00209 Rev. **
Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1333H
PRELIMINARY
Document History Page
Document Title: CY7C1333H 2-Mbit (64K x 32) Flow-Through SRAM with NoBL™ Architecture
Document Number: 001-00209
Orig. of
REV.
ECN NO. Issue Date Change
Description of Change
**
347377
See ECN
PCI
New Datasheet
Document #: 001-00209 Rev. **
Page 12 of 12
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